Abstract:- As technology improve the size will be reduced, and the power dissipated by the links of a network-on-chip (NoC) is starts to participate with the power dissipate by the other element of communication system, for example the routers and the network interfaces (NIs). We design an set of data encoding technique by different schemes to decrease the power dissipation by an links of NoC, which optimizing the on-chip communication system not only in terms of performance but also in terms of power. The idea presented in this paper is base on encoding the packets before they are inserted in to the network in such a way as to minimize both the switching action and the coupling-switching action in the NoC’s link which represent the main factor of power dissipation. These schemes were universal and transparent with respect to the construct NoC fabric that means this application will not require any change in the router and link of architecture. These will be carried in both artificial and real traffic scenario. These effective of the proposed scheme will tolerate to save the energy consumption and power dissipation without changing the performance degradation and with less area consumption in the NI.
Keywords: switching action, encoding, network-on-chip (NoC), low power, router, Network interfaces (NIs)
I. Introduction
Moving towards silicon technology node to the next results faster and more efficient gates but slower because there is a more power hungry wires. More than 50% of total dynamic power is dissipate in interconnection in current processor, and this was expected to increase more over in the next several years. Global interconnect length does not scale with smaller transistors and local wires. Chip size remains relatively constant because the chip function continues for instance the RC delay increases exponentially. The RC delay in a 1-mm worldwide wire at the smallest pitch is superior to the intrinsic delay of a two-input NAND fan-out. If the raw computation horsepower seems to be un-limited, thanks to the ability of instance more core’s in a single silicon chip, scalable issue occur, due to making an efficient and reliable communication among the increasing number of core’s, become the real problem. The NOC invent is documented as the most feasible way to tackle with scalable and variability issue that characterize the ultra-deep sub-micron-meter.
Now a days in the on-chip communication issue is relevant, in some of the case more relevant than commutating related issue. The communication sub-system more and more impacts the usual designed objective, and also includes cost (i.e., area of silicon), performances, dissipation of power, consumption of energy and reliability. As technology improves the size is reducing and more fraction of total power is budget of the complex in more core of the system-on-chip (SoC) this is because of communication sub-system.
II.
Motivation and Related work
Here we attentation on the
technique aim to minimize power dissipation by a network link. The power
dissipation in the network is relevant as that dissipation by NIs, routers and
it is giving that ordinary to increase the technology scale. We are
representing the set of encoding schemes for data which is in binary formate,
and it is operated at flit level, and an end-to-end basis, this allows us to
minimize the switching action and coupling switching action at the link of an
direction is traverse by a packet. This encoding schemes, were transparent by
respect to router execution, and they are presented, discussed in both
algorithmic-level and architectural level, it is assessed via the simulation in
the artificial, real traffic scenario. These analysis gives an different
aspects, metrics design, it include area of silicon, energy consumption and
dissipation of power. From the results we can conclude that with these proposed
encoding schemes that power will save and also energy will be save without changing
any major degradation in the performance in the NIs.
II.
Motivation and Related work
The accessibility of chips is growing every year. In next
few years, the accessibility of cores with 1000 cores is foreseen. Since the
focus of this paper is to decrease the power dissipation by link which
decreases the dynamic power, here we are going review the works in the area and
link power reduction. Also these will include some technique. They are, use of
shielding to increase line-to-line space
and repeater insertion. So above technique have large area consumption. One
method is the data encoding technique, its mainly focus is to reduce the link
power. The encoding technique’s is categorize in to two group. In 1st group we
are going to decrease the power by the self-switching action of the each bus
line and avoid the dissipation of power by coupling switching action.
These work concentrate on the
different component of the inter connection network such as NIs, router, and
link. Because these will reduce power dissipation by an link, in this paper, we
are going to brief the review some works in the region of link power reduction.
These include the technique that make use of shielding, which increase
line-to-line space and repeater inserted. They all increases the silicon chip
area. These encode scheme is an additional technique that is employed to reduce
dissipation of power in link. The data encoding technique has been classified
in to two class. In the first class, encoding technique concentrate on reducing
the power due to self-switching action of separate bus line while ignoring an
power dissipation due to their coupling-switching action. In these class, bus
invert (BI) and INC-XOR have been proposed for these case that casual random
data pattern is transmitte through the lines. On the other hand, gray code, T0,
working-zone encoding, and T0-XOR were suggest for the case of correlation data
pattern. Application particular approach have also been proposed
This class of encoding will not
be appropriate to be applied in the deep sub-micron meter technological node
where the coupling capacitance constitute an most important part of the total
inter-connect capacitance. This will cause the power consumption due to the
coupling-switching action to become a big fraction of the total power
consumption in the links, that making the aforementioned techniques, which
ignore such contributions, inefficient. The works in the second class
concentrate on reducing power dissipation through the reducing the
coupling-switching action. Among these schemes, the switching action is reduced
by using many additional control lines. For example, the data bus width grows
from 32 to 55. The techniques proposed in have a smaller number of control
lines but the complexity of their decoding logic is high. The technique
described as follows: first, the data are both odd inverted and even inverted,
and afterwards transmission is perform using these kind of inversion which
reduce more switching action. The coupling switching action it is reduced, this
is compared with another, so we use a simple decoder although achieving a
higher activity reduction.
The scheme presented is to reduce
the coupling switching action. In this method, encoder count the number of Type
I (Table I) transitions with a weighting coefficient of one and the number of
Type II transitions with the weighting coefficient of two. If the number is
larger than half of the link width, the inversion will be performed. In
addition to the complex encoder, the method only works on the patterns whose
full inversion leads to the link power reduction while not considering the
patterns whose full inversions may lead to high link power consumption. So the
link power reduction achieved through this technique is not as large as it
could be. This scheme was also based on the hop-by-hop technique.
In another coding technique
presented in, bunches of four bits are encoded with five bits. The encoded bits
were isolated using shielding wires such that the occurrence of the patterns
“101” and “010” were prevented. This way, no simultaneous Type II transitions
in two adjacent pair bits are induced. This technique effectively reduces the
coupling switching activity. Although the technique reduces the power
consumption considerably, it increases the data transfer time, and, hence, the
link energy consumption. This is due to the fact that for each four bits, six
bits are transmitted which increases the communication traffic. This technique
was also based on the hop-by-hop approach.
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